buffer (Total 40780 Patents Found)

A buffer flush controller, of a peripheral component interconnect-peripheral component interconnect bridge (PPB), includes a first compounding circuit, a first state machine, a second state machine, and a second compounding circuit. The buffer flush controller can maintain data consistency by efficiently controlling a ...
A scanning system includes a pair of buffer memories for alternately accumulating strings of signals which may contain bar coded label data. Candidate selection logic circuits examine incoming signals to generate a candidate signal when a string of signals satisfies gross logical tests. A control counter responds to th...
This data processing system includes a main memory which is shared by a plurality of central processor units (CPUs) which are also coupled in cascade in a closed circular path. Each CPU has a cache buffer memory and two sets of transfer registers for receiving and transmitting cancel request signals which identify cach...
An analog buffer, display device having the same and a method of drving the same are provided. The analog buffer applies an analog voltage to a load. The analog buffer includes a comparator and a transistor. The comparator is configured to compare an input voltage provided from an external device with the analog voltag...
The use of a composition of one or more aminoalcohol buffers in combination with one or more antimicrobial agents to disinfect contact lenses and preserve ophthalmic lens compositions is described. Ophthalmic lens solutions containing compositions of one or more aminoalcohol buffers in combination with one or more anti...
In a method or system for implementation of a transfer of data between two program elements of a process, a buffer object is provided between and linking two program elements. The buffer object comprises a buffer and control methods. A control method of a buffer object informs one of the linked program elements when th...
A packaging device includes a bottom plate and a mounting plate arranged above the bottom plate at a specific distance form the bottom plate. An article to be transported is placed on the mounting plate. A cushioning member is arranged in a space between the bottom plate and the mounting plate. The cushioning member pr...
A method for programming a multi-level-cell NAND flash memory device having plural memory cells is disclosed to reduce the programming time. The method comprises: programming each memory cell to a zero state, programming from the zero state to a first state by activating a first program signal and programming from the ...
A system and a method to avoid packet traffic congestion in a shared memory switch core, while dramatically reducing the amount of shared memory in the switch core and the associated egress buffers and handling unicast as well as multicast traffic. According to the invention, the virtual output queuing (VOQ) of all ing...
A method may be provided to operate a node of a radio access network communicating with a wireless terminal. The wireless terminal may be configured to provide a transmit buffer for data to be transmitted to the node during transmission time intervals, to transmit packets of the data from the transmit buffer to the nod...
Systems and methods can use client-side video buffer occupancy for enhanced quality of experience in a communication network. The systems and methods provided herein can drive changes in the communication system using control responses. Example control responses include responses for scheduling of packets under capacit...
A semiconductor wafer has a plurality of semiconductor die with contact pads for electrical interconnect. An insulating layer is formed over the semiconductor wafer. A bump structure is formed over the contact pads. The bump structure has a buffer layer formed over the insulating layer and contact pad. A portion of the...
This image forming apparatus includes: a development device configured to develop a toner image of a print image; an image carrier configured to transfer the toner image to a paper sheet; a print engine configured to control the development device and the image carrier; and a controller configured to control the print ...
A computer processing system method and apparatus having a processor employing an operating system (O/S) multi-task control between multiple user programs and which ensures that the programs do not interfere with each other, said computing processing system having a branch multiple page size prediction mechanism which ...
Uplink reporting and logical channel prioritization in multiflow operation is described. In some embodiments, uplink reporting for multiflow operation utilizes bearer level splitting where the UE associates bearers or logical channel groups (LCGs) with cells for uplink reporting. In some embodiments, uplink reporting f...
La présente invention a trait à un procédé pour le maintien de flux dans une mémoire tampon reliée à un contrôleur d'unité de stockage. Le contrôleur d'unité de stockage comporte des premier et deuxième compteurs qui servent au pilotage de l'instant de lecture de données à partir d'une mé...
A packet switch system having a buffer occupancy reduction mechanism for controlling data flow through switched nodes of the system to avoid congestion and reduce required buffer storage at the nodes. For an isochronous connection, buffers are initially allocated at each switching node connection to ensure listless tra...
A computer system having a checkpoint error recovery system. The computer system includes a first computer having a first memory and a second computer having a second memory and a buffer. The first and second memories are updated by memory updates that include an address specifying a location and data to be written to ...
A fixing bracket for a pressurized fluid buffer device such as a shock absorber or the like is formed as a single piece U-shaped bracket having a circular body portion for surrounding an outer cylinder of the shock absorber and opposed mounting flange portions for attachment to a vehicular chassis. At a location axiall...
A semiconductor buffer structure may include a silicon substrate and a buffer layer that is formed on the silicon substrate. The buffer layer may include a first layer, a second layer formed on the first layer, and a third layer formed on the second layer. The first layer may include Al x In y Ga 1-x-y N (0≦x≦1, 0...
A first output buffer having a large current driving capability and a second output buffer having a small current driving capability are connected in parallel between an input terminal and an external lead. The first and second output buffers each includes two CMOS inverters connected in series between the input termin...
A shared write back buffer for storing data from a data cache to be written back to memory. The shared write back buffer includes a plurality of ports, each port being associated with one of a plurality of processing units. All processing units in the plurality share the write back buffer. The shared write back buffer ...
A method utilizes a register file of an execution unit as a local instruction loop buffer to enable suitable algorithms, such as DSP algorithms, to be fetched and executed directly within the execution unit, and often enabling other logic circuits utilized for other, general purpose workloads to either be powered down ...
An approach is provided is provided in which a computing system matches a writeback instruction tag (ITAG) to an entry instruction tag (ITAG) included in an issue queue entry. The writeback ITAG is provided by a first of multiple load store units. The issue queue entry includes multiple ready bits, each of which corres...